VLSI Systems Design Laboratory (1SH).

Summer, 2018

Lab: COE Computer Center(Snell #208)

Class Data & Time: TBD

Instructor: Dr. Yong-Bin Kim  (ybk@ece.neu.edu)

TA: Gyunam Jeon (gjeon@ece.neu.edu)

Office hours: TBD (140 The Fenway R306) 

Please check this web-page regularly. Don't be late to submit the report, and attend on your reserved date.

 Course Goals

To study layouts of CMOS combinational and sequential circuits.
To utilize switch-level and circuit-level simulators for the logic verification and timing simulation.

EECE 4524 must be taken concurrently.

 Course Grading

Attendance

The correctness of the simulation

The organization of the report (Student Laboratory Report Format).

Confirm your results with the TA before leaving.

 Lab Section

Section  (Day & Hour : TBD)

 One group has to consist of two students, and share one workstation with each other.

Each student has to submit a report. (Not a report per one group.)

 Reference Materials for Lab

Basic Unix Tutorial.

 

 Hspice materials.

Getting Started with Hspice on COE system.              How to Print in Hspice

 

 Cadence materials.

Getting Started with Cadence on COE system.  


Hspice Netlist Extraction with Cadence

Schematic Entry with Composer                                  How to Print in Cadences

Analog Artist with HSPICE 

Introduction to Layout and DRC 

LVS and Parasitic Extraction using Calibre 

 Other References

IC Design Flow  and   Layout Example  (These materials help you to understand the Circuit Layout)

 Lab Materials

Please read all the above references before each lab.

 Lab 1 (1 week) : Lab #1 Guideline 

 Lab 2 (2 weeks) : Lab #2 Guideline  &  frame1.sp  frame2.sp  frame3.sp  

Before this Lab 2, read "Schematic Entry with Composer" which introduces basic things for Cadence, especially schematic  editor.

    FAQ) Tphl and Tplh is not rirsing and falling time but the propagation delays from input to output.

              Hence, Tphl is the delay when Input changes Low->High and Output changes High->Low.

              You can measure the time difference between Input and Output at half VDD voltage (in our circuit, 0.55V).

              Tplh is the delay when Input changes High->Low and Output changes Low->High.

              You can measure the time difference between Input and Output at half VDD voltage (in our circuit, 0.55V).

 Lab 3 (1 weeks) : Lab #3 Guideline  &  lab3-1.tar & latch_frame.sp & flip_flop_frame.sp

 Lab 4 (1 weeks) : Lab #4 Guideline  & FA_frame.sp &  4RCA_frame.sp   

 Lab 5(1 weeks) : Lab #5 Guideline  & FA_frame.sp &  4RCA_frame.sp   

 Lab 6 (1 weeks) : Lab #6 Guideline  & dynamic_frame.sp & trans_frame.sp   

Dr. Yong-Bin Kim. Department of Electrical and Computer Engineering
327 Dana Research Center, 360 Huntington Avenue, Boston, MA 02115, USA
Tel: (617) 373-2919, Fax: (617) 373-8970
 ybk@ece.neu.edu