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DTSTART;TZID=America/New_York:20220209T103000
DTEND;TZID=America/New_York:20220209T120000
DTSTAMP:20260611T221604
CREATED:20220209T213347Z
LAST-MODIFIED:20220209T213347Z
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SUMMARY:ECE Seminar: Qiushi Guo
DESCRIPTION:ECE Seminar: Emergent Active Photonic Platforms for Next-generation Mid-infrared and Ultrafast Photonics \nQiushi Guo \nLocation: 442 Dana or Zoom Link \nAbstract: As two basic properties of light\, wavelength and timescale are central to numerous photonic applications. Compared to visible and near-infrared\, the longer wavelength mid-infrared spectral regime contains unique thermal visual information and chemical fingerprints of the environment.  On a different front\, femtosecond light sources and systems can enable ultrafast information processing\, sensing\, and computing. Yet\, current chip-scale photonic devices and systems are facing tremendous challenges in detecting\, generating\, and processing light of long wavelength and ultrashort timescale. Overcoming these challenges requires new materials and clever device architectures\, and these technologies stand poised to revolutionize fields such as biomedical sensing\, free-space communication\, and photonic computing in both classical and quantum domains. \nIn this talk\, I will show that by engineering the carrier and nonlinear dynamics in emergent active photonic materials\, we can detect photons beyond the regimes accessible to conventional laser sources and detectors\, and process information in an ultrafast manner. In the first half of my talk\, I will first briefly introduce the discovery of black phosphorus (BP) mid-infrared photonics\, highlighting the world’s first BP mid-infrared detectors with high internal gain\, as well as BP’s electrically tunable spectral response due to its unique bandgap tunability. Then\, I will discuss a new strategy for detecting longer wavelength mid-infrared radiations at 12 µm. This is achieved by harnessing the intrinsic mid-infrared plasmons in large-scale graphene. \nThe second half of my talk will cover my recent work on integrated lithium niobate (LN) ultrafast photonics in both classical and quantum domains. I will discuss the realization of ultra-strong nonlinear optical interactions and dynamics in dispersion-engineered and quasi-phase-matched integrated LN devices\, which have enabled 100 dB/cm optical parametric amplification\, ultra-wide bandwidth quantum squeezing\, as well as femtosecond and femtojoule all-optical switching. Finally\, I will outline promising pathways toward realizing chip-scale ultrafast light sources and microsystems for on-chip spectroscopic sensing\, mid-infrared free-space communication\, coherent all-optical computing\, and next-generation thermal vision technologies. \nBio: Dr. Qiushi Guo is currently a postdoctoral scholar at the California Institute of Technology with Prof. Alireza Marandi. He received his Ph.D. in Electrical Engineering from Yale University in Dec. 2019\, advised by Prof. Fengnian Xia. He received his M.S. degree in Electrical Engineering from the University of Pennsylvania in 2014\, and his B.S. degree in Electrical Engineering from Xi’an Jiaotong University in 2012. Qiushi is the winner of the 2021 Henry Prentiss Becton Graduate Prize for his exceptional research achievements at Yale University. His research interests include integrated nonlinear and quantum photonics\, mid-infrared photonics\, and 2-D materials optoelectronics. He has published 36 peer-reviewed research papers in leading scientific journals with citations more than 2700 times. He is serving on the editorial board of the journal Micromachines.
URL:https://ece.northeastern.edu/event/ece-seminar-qiushi-guo/
LOCATION:442 Dana\, 360 Huntington Ave\, 442 DA\, Boston\, MA\, 02115\, United States
GEO:42.3387508;-71.0923044
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DTSTART;TZID=America/New_York:20220209T120000
DTEND;TZID=America/New_York:20220209T130000
DTSTAMP:20260611T221604
CREATED:20220208T001833Z
LAST-MODIFIED:20220208T001833Z
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SUMMARY:ECE Seminar: Derya Aksaray
DESCRIPTION:ECE Seminar: Reinforcement Learning for Dynamical Systems with Temporal Logic Specifications \nDerya Aksaray \nLocation: 442 Dana or Zoom Link \nAbstract: In many applications\, dynamical systems such as drones\, mobile robots\, or autonomous cars need to achieve complex specifications on their trajectories which may include spatial (e.g.\, regions of interest)\, temporal (e.g.\, time bounds)\, and logical (e.g.\, priority\, preconditions\, concurrency among tasks) requirements. As these specifications become more complex\, encoding them via algebraic equations become intractable. Alternatively\, such specifications can be compactly expressed and used in control synthesis by utilizing the framework of temporal logics. In this talk\, I will address the problem of learning optimal control policies for satisfying temporal logic (TL) specifications in the face of uncertainty. Standard reinforcement learning (RL) algorithms\, which aim to maximize the expected sum of discounted rewards\, are not directly applicable when the objective is to satisfy a TL specification. To overcome this limitation\, I will formulate an approximate problem that can be solved via reinforcement learning and present the suboptimality bound of the proposed solution. Then\, I will consider the case where a TL specification is given as the constraint rather than the objective and present a novel approach for satisfying the TL constraint with a desired probability throughout the learning process. I will motivate this part by multi-use of autonomous systems\, e.g.\, a drone executing a pick-up and delivery mission as its primary task (constraint) while learning to fly over regions of interest (aerial monitoring) as its secondary task (objective). Finally\, I will conclude my talk by discussing some future directions toward the resilience and safety of autonomous systems with complex specifications. \nBio: Derya Aksaray is currently an Assistant Professor in the Department of Aerospace Engineering and Mechanics at the University of Minnesota (UMN). Before joining UMN\, she held post-doctoral researcher positions at the Massachusetts Institute of Technology from 2016-2017 and at Boston University from 2014-2016. She received her Ph.D. degree in Aerospace Engineering from the Georgia Institute of Technology in 2014. Her research interests lie primarily in the areas of control theory\, formal methods\, and machine learning with applications to autonomous systems and aerial robotics.
URL:https://ece.northeastern.edu/event/ece-seminar-derya-aksaray/
LOCATION:442 Dana\, 360 Huntington Ave\, 442 DA\, Boston\, MA\, 02115\, United States
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DTSTART;TZID=America/New_York:20220209T150000
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SUMMARY:ECE PhD Proposal Review: Mengting Yan
DESCRIPTION:PhD Proposal Review: Circuit Design Methods for Temperature-based Hardware Trojan Detection and Parametric Frequency Division in Next-Generation Systems-on-a-Chip \nMengting Yan \nLocation: Zoom Link \nAbstract: With the increasing costs and globalization in the semiconductor industry over the past years\, the ongoing trends to disperse integrated circuit (IC) design\, fabrication and testing tasks among different design centers and manufacturers are becoming more common and inevitable. As a soaring number of ICs are fabricated around the world\, the increasing risks associated with hardware Trojan (HT) insertions have been identified as a growing concern in military systems\, medical applications\, wireless cryptography\, etc. This research introduces an integrated system-level on-chip countermeasure to malicious HT insertions\, which is founded on power sensing and integrated circuit design. The approach addresses the corresponding design considerations of analog temperature sensors\, on-chip quantization of signals and machine learning-based data analysis.\nAn on-chip temperature-based HT detection system is proposed in the first part of this dissertation research. The approach to detect inserted HTs relies on thermal profiling of the circuit-under-test (CUT) and side-channel analysis of the obtained thermal data. Hence\, a system that includes the CUT\, modeled HT\, temperature sensing circuitry and an on-chip ADC will be implemented and evaluated through simulations and measurements. On-chip electro-thermal coupling is modeled as part of the simulation technique\, which associates local thermal activities with circuit-level power consumption using a standard electrical simulator. To monitor the thermal profiles on chips with high sensitivity to local temperature changes and the resilience to flicker noise\, a fully-differential temperature sensor equipped with a chopping mechanism has been designed in 130-nm CMOS technology\, which has a sensitivity of 840 V/°C over a linear dynamic range of ±1°C. The simulated temperature sensor output in the presence of noise and process variations is quantized by an ideal ADC model and processed using principal component analysis (PCA)\, which allows to determine the minimum detectable Trojan power and the design requirements for the on-chip ADC. With a modeled 8-bit ideal ADC\, the proposed HT detection system shows a detection rate of 100% with a Trojan power down to 2.4 µW within the thermal profile of a CUT consuming 508 µW. A prototype 8-bit 1 MS/s SAR ADC was designed in 130-nm CMOS technology\, fabricated\, and tested. The measured effective number of bits (ENOB) is 7.27 bits up to the Nyquist frequency with a power consumption of 103.2 µW from a 1.2 V supply.\nAnother part of this dissertation research addresses the need for low-power 2:1 frequency division at sub-6 GHz frequencies for radio frequency (RF) systems-on-a-chip (SoCs). In particular\, a differential 2:1 parametric frequency divider (PFD) with an output frequency of 2.4 GHz and an input voltage range of 450-890 mV at 4.8 GHz is being designed in 65-nm CMOS technology\, which mainly consists of passive on-chip components and consumes zero static power. The proposed PFD is the first on-chip CMOS implementation for sub-6 GHz applications\, which balances the trade-offs among frequency range\, power consumption\, and chip area constraints. As an important part of this dissertation\, the performance of the proposed PFD will be validated with measurements of a prototype chip fabricated in standard 65-nm CMOS technology.
URL:https://ece.northeastern.edu/event/ece-phd-proposal-review-mengting-yan/
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