BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Department of Electrical & Computer Engineering - ECPv6.17.5//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:Department of Electrical & Computer Engineering
X-ORIGINAL-URL:https://ece.northeastern.edu
X-WR-CALDESC:Events for Department of Electrical & Computer Engineering
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20220313T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20221106T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20230312T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20231105T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20240310T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20241103T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230522T103000
DTEND;TZID=America/New_York:20230522T113000
DTSTAMP:20230522T211916Z
CREATED:20230522T211916Z
LAST-MODIFIED:20230522T211916Z
UID:6352-1684751400-1684755000@ece.northeastern.edu
SUMMARY:Mengting Yan's PhD Dissertation Defense
DESCRIPTION:“Integrated Circuit Design Methods for Temperature-based Hardware Trojan Detection and Parametric Frequency Division in Next-Generation Systems-on-a-Chip” \nCommittee Members:\nProf. Marvin Onabajo (Advisor)\nProf. Yong-bin Kim\nProf. Yunsi Fei \nAbstract:\nNew needs for next-generation systems-on-a-chip (SoC) are emerging as the trend of globalization in the semiconductor industry becomes increasingly ubiquitous and the demand for low-power Internet-of-Things (IoT) devices continues to soar. Among various research directions\, this dissertation focuses on enhancing hardware security and on providing low-noise frequency sources for next-generation SoCs. Within this scope\, the described research addresses the challenge to improve on-chip anomaly detection capabilities\, and separately lays a foundation for the design of circuits to reduce the phase noise of on-chip oscillators. \nIn the first part of this dissertation\, an on-chip temperature-based Hardware Trojan (HT) detection system is introduced. The approach to detect inserted HTs relies on thermal profiling of the circuit under test (CUT) and side-channel analysis of the obtained temperature data. On-chip electrothermal coupling is modeled as part of a simulation technique that associates local thermal activities with circuit-level power consumption using a standard electrical simulator. To monitor the thermal profiles on chips with high sensitivity to local temperature changes as well as to enhance the resilience to flicker noise\, a fully-differential temperature sensor equipped with a chopping mechanism has been designed in 130-nm complementary metal-oxide-semiconductor (CMOS) technology\, which has a sensitivity of 840 V/◦C. The simulated temperature sensor output in the presence of noise and process variations is quantized by an analog-to-digital converter (ADC) model and processed using principal component analysis (PCA)\, which allows to determine the minimum detectable Trojan power and the design requirements for the on-chip ADC. With a modeled 8-bit ADC\, simulations of the HT detection system reveal a detection rate of 100% with a Trojan power down to 2.4 μW within the thermal profile of a CUT consuming 508 μW. A prototype 8-bit 1 MS/s successive approximation register (SAR) ADC for such a system was designed in 130-nm CMOS technology\, fabricated\, and tested. The measured effective number of bits (ENOB) is 7.27 bits up to the Nyquist frequency\, with a power consumption of 103.2 μW from a 1.2 V supply. Furthermore\, a 3-step analog calibration loop has been designed to compensate for the voltage offsets within the sensor circuits in the presence of device mismatches and process-temperature variations. The calibration loop settles within 300 μs to complete the offset calibration\, such that the input-referred offset has a standard deviation of 5.86 μV based on Monte Carlo simulations. \nIn the second part of this dissertation\, the on-chip realization of a parametric frequency divider (PFD) is explained. The low-power 2:1 frequency division at sub-6 GHz plays a critical role in on-chip phase noise reduction systems that exhibit nonlinear operations\, indicating promise for future integration into radio frequency (RF) SoCs. In particular\, the first current-driven PFD with an output frequency of 2.4 GHz is introduced\, which consists of three major blocks: (1) a custom PFD driver stage with a buffer to ease input driving\, (2) a purely passive PFD core with inductor-capacitor (LC) resonators\, and (3) an output driving stage with embedded band-pass filtering that suppresses undesirable output harmonics. A prototype PFD chip was fabricated in standard 65-nm CMOS technology\, and the corresponding measurement results are presented to characterize the performance of the new PFD. The minimum required supply voltage for the PFD driver is 1.4 V with an input frequency of 4.8 GHz\, whereas the PFD has an operating frequency range from 4.5 GHz to 5.1 GHz with a supply voltage of 1.5 V. To the best of the author’s knowledge\, the proposed PFD is the first on-chip CMOS implementation for sub-6 GHz applications\, which balances the trade-offs among frequency range\, power consumption\, and chip area constraints.
URL:https://ece.northeastern.edu/event/mengting-yans-phd-dissertation-defense/
LOCATION:MA
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230526T090000
DTEND;TZID=America/New_York:20230526T100000
DTSTAMP:20230522T211659Z
CREATED:20230522T211659Z
LAST-MODIFIED:20230522T211659Z
UID:6350-1685091600-1685095200@ece.northeastern.edu
SUMMARY:Yuezhou Liu's PhD Proposal Review
DESCRIPTION:Committee Members:\nProf. Edmund Yeh (Advisor)\nProf. Stratis Ioannidis\nProf. Lili Su\nProf. Carlee Joe-Wong \nAbstract:\nSignificant advances in edge and mobile computing capabilities enable machine learning to occur at geographically diverse locations in networks\, e.g.\, cloud\, edge\, and mobile devices. The training data needed in those learning tasks may not be fully generated locally. Moreover\, some promising distributed learning paradigms enable devices to collaboratively train a model\, which requires communication among the devices for exchanging necessary information. Thus\, optimizing network strategies for the transmission/exchange of ML/AI ingredients (e.g.\, input data\, model parameters\, gradients) is important for facilitating efficient in-network distributed ML. While there exist many works that use ML to optimize network operation strategies\, few works study optimized networks that boost ML performance. This dissertation tries to fill the gap by studying several network optimization problems for distributed ML. Different from classic network optimization problems for data delivery or edge computing that optimize energy consumption\, delay\, throughput\, etc.\, we also pay attention to ML-related metrics such as model accuracy and training convergence time. \nWe first propose an experimental design network paradigm\, wherein learner nodes train possibly different ML models via consuming data streams generated by data source nodes over a network. We formulate this problem as a social welfare optimization problem in which the global objective is defined as the sum of experimental design objectives of individual learners\, and the decision variables are the data transmission strategies subject to network constraints. We show that\, assuming Bayesian linear regression models and Poisson data streams in steady state\, the global objective is continuous DR-submodular\, which enables the design of efficient approximate algorithms with approximation guarantees. We will further extend our framework to incorporate more practical ML applications\, such as ML with arbitrary nonlinear models. \nThe second half of this dissertation studies network optimization for Federated learning (FL)\, a distributed paradigm for collaboratively learning models without having clients disclose their private data. We propose to use caching for improving FL efficiency concerning the total model training time for convergence. Instead of having all clients download the latest global model from a parameter server\, we select a subset of clients to access\, with smaller delays\, a somewhat stale global model stored in caches. We propose CacheFL — a cache-enabled variant of FedAvg\, and provide theoretical convergence guarantees in the general setting where the local data is imbalanced and heterogeneous. With this result\, we determine the caching strategies that minimize total wall-clock training time at a given convergence threshold for both stochastic and deterministic communication/computation delays.
URL:https://ece.northeastern.edu/event/yuezhou-lius-phd-proposal-review/
LOCATION:MA
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230526T123000
DTEND;TZID=America/New_York:20230526T133000
DTSTAMP:20230522T211528Z
CREATED:20230522T211528Z
LAST-MODIFIED:20230522T211528Z
UID:6347-1685104200-1685107800@ece.northeastern.edu
SUMMARY:Guillem Reus Muns' PhD Dissertation Defense
DESCRIPTION:“AI for communication and sensing in RF environments” \nCommittee Members:\nProf. Kaushik Chowdhury (Advisor)\nProf. Stratis Ioannidis\nProf. Hanumant Singh \nAbstract:\nThe recent growth of Internet of Things (IoT)\, as well as other new\nrevolutionary applications utilizing wireless spectrum are leading the way towards the realization of next-generation wireless systems that jointly utilize communications and sensing. However\, such systems offer many degrees of freedom\, and optimizing them for a specific task is difficult to accomplish with deterministic and classical approaches. For this reason\, data-driven and AI-based methods have been pursued actively by the research community\, as they are able to find solutions that often come close to or exceed the performance of the deterministic counterparts with fractional design complexity. This thesis presents\, through real systems and with experimental validation\, our progressive efforts in four broad areas\, where AI enables the operation of aerial and terrestrial systems that combine sensing and communications. The following key use cases with distinct contributions are investigated: \ni) Sensing-aided communications for air and ground systems. First\, we present a UAV communication method that defines constellation points in space that map to transmitter frequency bands and are detected at the Base Station using millimeter wave sensors. Second\, we explore alternative vehicle-to-infrastructure mmWave beamforming methods\, leveraging a) vehicle position and velocity estimation using in-band standard compliant 802.11ad radar and b) camera images and GPS location information. \nii) Signal classification using communication signals\, where we propose a) a UAV classification method using uniquely UAV-transmitted signals and b) an RF fingerprinting technique that improves class separation by combining triplet loss with regular classification techniques. \niii) ‘SenseORAN’\, a revolutionary architectural design that aims to reuse the cellular infrastructure for sensing purposes in order to address spectrum access challenges in the CBRS band. This is enabled by Open Radio Access Network (O-RAN)\, a cellular architecture concept that promotes virtualized RANs where disaggregated components are connected via open interfaces and supports intelligent controllers running custom logic. iv) ‘AirFC’\, an over-the-air computation method that implements fully connected neural networks inference leveraging multi-antenna wireless systems.
URL:https://ece.northeastern.edu/event/guillem-reus-muns-phd-dissertation-defense/
LOCATION:Admissions Visitor Center (West Village F)
END:VEVENT
END:VCALENDAR