VSIPL++ Interface For FPGAs


VSIPL++ is the C++ version of the Vector/Signal/Image Processing Library, a library of C and C++ routines for simply and efficiently writing programs to perform standard signal processing functions. The VSIPL Forum oversees the development of the VSIPL standard, along with the HPEC-SI working group. Together, they have released the VSIPL++ standard. A reference implementation of VSIPL++ is available from the HPEC-SI page under the "Implementation and Specification Development" section. Commercial implementations are available from vendors such as Codesourcery .

Our project seeks to create a framework of C++ objects which can ease the inclusion of hardware algorithm accelerators (specifically those targeted for FPGAs) in VSIPL++ code development. With our framework, FPGA board vendors, who create a library of VSIPL++ algorithms that run on their own products, can make those accelerators available to a VSIPL++ programmer through a simple, standardized interface. The VSIPL++ programmer need only change a few lines of code in order to take advantage of these accelerators - no knowledge of FPGA algorithm design is necessary. The emphasis is on providing high-performance solutions with minimal overhead.

Processing Framework

In VSIPL++, the programmer interacts with processing objects that realize algorithms in software. In our framework, the programmer still works with processing objects, but in addition to running in software, the computation can also be run on a FPGA. This is facilitated by the introduction of VSIPL++ hardware objects that encapsulate the hardware specific information and manage communication and control of the FPGAs. Every FPGA board has its own hardware class that is derived from the same virtual base class. The base class defines a common interface for all hardware objects. A particular FPGA board's hardware class contains all of the vendor and model specific information needed to communicate with its corresponding FPGAs, including the necessary APIs and bitstream locations and characteristics. The FPGA box shown at the upper right of the figure represents the reconfigurable hardware.

Our framework incorporates a Run Time Resource Manager (RTRM) shown at the bottom of the figure . The RTRM exists as a separate program, either run on a separate CPU or as a distinct process in a multitasking environment. The RTRM maintains the pool of available reconfigurable hardware in a shared environment and distributes them to VSIPL++ applications upon request. The manager controls access to shared hardware and brokers the assignment of tasks to particular FPGA hardware. If no reconfigurable hardware is available that can perform the requested algorithm, the RTRM will respond appropriately so that the processing object can transparently default to performing the computation in software.

Project Status

Our initial work was a simplified version of the framework that did not include the resource manager. The goal was to demonstrate that the same VSIPL++ application could easily be adapted to several different hardware platforms. This early version implements a master/slave model with a general purpose processor (GPP) acting as a master, and the FPGA hardware as the slave. The GPP provided the functionality of the VSIPL++ calling program as well as the RTRM.

This initial processing framework has been shown to be effective for harnessing FPGA resources in an environment where one VSIPL++ program accesses a predetermined FPGA resource. We will continue to add more drop-in replacements for processing algorithms, as well as additional hardware classes and bitstreams.

A more fully realized implementation of the RTRM and removing programmer involvement in hardware allocation altogether is under development. Currently, a few simple changes in headers and constructor calls are required to use a different hardware class; we are moving towards using different hardware dynamically based on availability with no application level coding changes required. Requests to the RTRM will be serviced by returning a generic hardware pointer as well as a reference to a dynamically loaded library that contains the code needed to map the processing object requests onto the specific hardware API.

We currently have VSIPL++ API support for the Wildcard II from Annapolis Microsystems , the MCJ6 FCN from Mercury Computers , and the Cray XD1 . Support for other hardware platforms is planned.

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Maintained by Miriam Leeser
Last modified: Friday July 14 10:31:40 EST 2006