The paper shows that `GAg' branch architecture performs as effective as the `PAs' when the difference in the penalty of misfetch and misprediction is taken into account, which should be. A slightly bigger `GAg'(which is also smaller and easier to implement than smaller `PAs') is shown to be better than the `PAs'.
The paper proposes an alternate architecture dispensing with the BTB. This architecture from less performance, unless profiling is used for indirect jumps. Considering the pace of VLSI technology, a BTB can be accommodated, even if not with much ease. If the proposal of having a smaller BTB for indirect branches alone can be proved to be effective, this proposed architecture is a good and effective alternative to the BTB architecture.
The paper does not take into account wide issue processors. The model requires that instructions have the readily usable information of whether they are branch instructions, which is not very realistic. Calder et al. propose having entries in the instruction cache, but again this technique suffers from being compulsory, that the first time an instruction is fetched, the information is not available.
The new thoughts the paper has brought are good alternatives, although they do not realize to the potential of replacing the BTB architecture. Further research has been done and can be done in the future based on this paper. Particularly, the `Decoupled Prediction and Fall through' is being considered as an effective alternative like in [6, 2]. Also, similar architectures to the ones proposed are being used in current processors. The Intel Pentium and P6 use a scheme similar to the `Only Taken Allocate' and the PowerPC 604 uses a scheme similar to the `Decoupled Prediction and Fall through'.