The performance of the different caches and prediction sources have been compared using trace-driven simulation. The direct-mapped cache, the two way set-associative cache, the column associative cache and the predictive sequential associative cache (with prediction sources - ``Eff'' and ``XOR-5-5'') have been simulated. Two programs - eqntott and compress from the SPECint92 benchmark suite have been simulated to measure the cache performance. The ATOM [9] tool on the Alpha AXP-21064 (stimpy@nuvlsi.ece) has been used for instrumenting the programs. ATOM requires an instrumentation file and an analysis file. Atom links the analysis routines with the reloadable compiled code (.rr files) as per the instrumentation file. It locates the analysis routines such that, the natural order of the program is not disturbed and ensures, that the simulation is very natural to the supposed hardware.
The high miss rates of data caches warrants higher associativity and requires caches with the lesser miss rates than direct-mapped caches. The primary concern of the CA cache, PSA cache and such other caches has been first-level data caches. Also, instruction cache misses can be reduced by techniques like profiling and other software techniques [8]. Calder et al. [1] also suggest that the ``Eff'' technique can be used with instruction caches. An 8 KBytes data cache with 32 byte cache line is assumed. A write-around or no-store allocate write policy is implemented as this is the case in most processors. Stores and Loads are measured separately, as this is a no-store allocate cache.