Please check this web-page regularly. Don't be late to submit the report, and attend on your reserved date.

 Course Goals

To study layouts of CMOS combinational and sequential circuits.
To utilize switch-level and circuit-level simulators for the logic verification and timing simulation.

EECE 7420 must be taken concurrently.

 Course Grading

Attendance

The correctness of the simulation

The organization of the report (Student Laboratory Report Format).

Confirm your results with the TA before leaving.

 Lab Section

Section  (Day & Hour : Tuesday 5:10 pm to 6:20 pm or/and Wednedesday 5:00 pm to 6:30 pm)

 One group has to consist of two students, and share one workstation with each other.

Each student has to submit a report. (Not a report per one group.)

 Reference Materials for Lab

 Cadence materials.

Getting Started with Cadence on COE system.  


Hspice Netlist Extraction with Cadence

Schematic Entry with Composer                                  How to Print in Cadences

Analog Artist with HSPICE 

Introduction to Layout and DRC 

LVS and Parasitic Extraction using Assura 

 Other References

IC Design Flow  and   Layout Example  (These materials help you to understand the Circuit Layout)

 Lab Materials